Application Area Specific System Level Fault Models: A Case Study with a Simple NoC Switch

In this paper we make a case for moving the level of test pattern generation for fabrication faults to the system level. Like many other researchers we feel it is necessary to handle the growing size and complexity of testing of digital systems. As the first step in this direction, system level fault models must be defined. Unlike logic level stuck-at fault models it is hard to define general fault models at the system level. In this paper, we argue that it is practical and efficient to define application area specific system level fault models. A NoC switch is used as a case study to explain the idea of such system level fault models. We propose two metrics to evaluate the efficiency of system level fault models. We also propose a method for generation of test patterns using system level fault models. Our initial evaluation experiments show that the test patterns generated using the proposed system level faults have much higher fault coverage than purely random test patterns but lower coverage than test pattern generated on actual implementation using the PODEM algorithm. The results of this case study demonstrate that application area specific system level fault models have a good potential for testing complex systems.